1. Field of Invention
The present invention relates to a control circuit of First-In-First-Out memory and It's control method, more particularly to a empty flag generator which generates an empty flag indicating that there is no data in the FIFO memory.
2. Discussion of Related Art
FIFO memory is a kind of memory devices used in a multi-processor, a serial communication network, fax, a modem and the like as a buffer. In the FIFO memory, input and output of data is implemented in a different way from general memory devices. That is to say, first inputted data is outputted first as the term "FIFO" means.
Information of the size of data stored in FIFO memory is required for using the FIFO memory]. Generally, a FIFO memory control circuit detects the present size of data stored in FIFO memory by comparing an address of a memory region which the data has been written lately from address of memory region which the data has been read lately.
For an effective control of FIFO memory, it is necessary to detect an empty state or full state of FIFO memory. Namely, unnecessary access to read data is avoided by detecting that there is no data in FIFO memory as well as that FIFO memory is full of data.
FIFO memory is equipped with an empty flag generator for an Empty Flag and a full flag generator for Full Flag. The empty flag generator generates an empty flag when a write address is identical to a read address. Because, the fact that the write address is identical to the read address means all the data in FIFO memory is outputted.
FIG. 1 shows a block diagram of a FIFO memory control circuit according to a related art. The FIFO memory control circuit is disclosed at U.S. Pat. No. 4,873,666 end invented by Martin C. Lefebvre, Carmine A. Ciancibello, and Youssef A. Geadah.
Referring to FIG. 1, a write counter 101 and a read counter 102 generate a write address WR.sub.-- ADD and read address RD.sub.-- ADD, respectively. The write address WR.sub.-- ADD is inputted to a write register 103, a comparator 106 and a multiplexer 107. The read address RD.sub.-- ADD is inputted to a read register 104, a comparator 105 and the multiplexer 107.
The comparator 105 generates an empty flag EF by comparing the write address WR.sub.-- ADD to the read address RD.sub.-- ADD. The other comparator 106 generates a full flag by comparing the write address WR.sub.-- ADD to the read address RD.sub.-- ADD.
The multiplexer 107 transfers either an inputted read address RD.sub.-- ADD or an inputted write address WR.sub.-- ADD to FIFO memory 108. When write address WR.sub.-- ADD is generated, data is inputted to FIFO memory 108 with the write address WR.sub.-- ADD. Because the write address WR.sub.-- ADD is generated for the writing of data in FIFO memory 108. In this case, a FIFO memory control circuit 100 controls FIFO memory 108 in order to have data which is inputted to FIFO memory 108 to be written in a memory region designated by the corresponding write address WR.sub.-- ADD.
Otherwise, when the read address RD.sub.-- ADD is generated, there occurs no data input. Because the read address RD.sub.-- ADD is generated for reading data form FIFO memory 108. In this case, the FIFO memory control circuit 100 controls FIFO Memory 108 in order to have data in memory region which is designated by a corresponding read address RD.sub.-- ADD be outputted.
In the related art, an empty flag is generated by detecting that every bit of write address is identical to every bit of read address. Namely, An empty flag is generated by detecting that a read address is identical to a write address.
A speed of generating an empty flag increases provided that a pre-empty flag is generated in a clock before a read address which is identical to a write address and that an empty flag is generated as soon as a read address identical to the write address is generated after an elapse of one clock.